Electrostatic discharge (ESD) may cause damage to electronic products and it is difficult to be solved. At present, the most commonly used ESD protection structure for semiconductor integrated circuits is GGMOS (Ground Gate MOSFET). A GGMOS device includes a low-voltage MOS (namely ordinary MOS transistor), an LDMOS (Lateral Diffusion MOSFET) and a DDDMOS (Double Diffusion Drain MOSFET), etc. Wherein, the low-voltage MOS is mainly used as an ESD protection structure for low-voltage circuits, while the LDMOS and DDDMOS are used as ESD protection structures for high-voltage circuits.
Currently, the transistors used as ESD protection structures are mainly N-type MOS transistors. Therefore, the examples of low-voltage MOS, LDMOS and DDDMOS described in the present application are all N-type MOS transistors.
Refer to FIG. 1, which is a schematic diagram showing an existing N-type LDMOS used as an ESD protection structure. Wherein, a P-type well 12 is formed on a P-type substrate 10, and an N-type lightly doped region 11 (i.e. N-type well) is formed in the P-type well 12. Isolation structures 131, 132 are formed in the P-type well 12; an isolation structure 133 is formed in the N-type lightly doped region 11; an isolation structure 134 is formed in the N-type lightly doped region 11 and/or the P-type well 12; the isolation structures 131, 132, 133, and 134 are structures such as LOCOS (Local Oxidation of Silicon) structures or STI (Shallow Trench Isolation) structures. A gate 14 is formed on the P-type well 12, wherein one side of the gate is on the P-type well 12 and the other side is on the isolation structure 133; spacers 15 are formed on both sides of the gate 14; wherein the material of the gate 14 is such as polysilicon, and the material of the spacers 15 is such as silicon nitride. A P-type heavily doped region 161 used as the picking-up terminal of the P-type well 12 is formed between the isolation structures 131 and 132 in the P-type well 12. An N-type heavily doped region 162 used as a source is formed between the isolation structure 132 and one of the spacers 15 of the gate 14 in the P-type well 12. An N-type heavily doped region 163 used as a drain is formed between the isolation structures 133 and 134 and is close to the isolation structure 133 in the N-type lightly doped region 11. And a P-type heavily doped region 164 is formed between the isolation structures 133 and 134 and is close to the isolation structure 134 in the N-type lightly doped region 11. When the LDMOS device is used as an ESD protection structure for a semiconductor integrated circuit, the P-type heavily doped region 161 and the N-type heavily doped region (source) 162 are grounded (i.e. GND), the gate 14 is connected to an interior circuit (or grounded via a resistor), and the N-type heavily doped region (drain) 163 and the P-type heavily doped region 164 are connected to an input/output bonding pad, namely to receive electrostatic charge via the input/output bonding pad.
To simplify, some details such as a gate oxide layer under the gate, pad oxide layer on the side walls and bottom of trenches, and a possible epitaxial layer on the substrate are not described and shown in FIG. 1.
In the LDMOS device shown in FIG. 1, an additional P-type heavily doped region 164 is formed on the side of the drain 163 away from the gate 14 to form a parasitic silicon controlled rectifier to improve the ESD protection capacity thereof.
Refer to FIG. 2 and FIG. 3, when ESD occurs, the parasitic silicon controlled rectifier works as follows:
After positive electrostatic charge enters the LDMOS device shown in FIG. 1 via the input/output bonding pad, the potential of the N-type lightly doped region 11 will rise. And generally, the voltage breakdown occurs at the border of the N-type lightly doped region 11 formed below the channel of the LDMOS device, namely at the early failure point A shown in FIG. 2.
The breakdown current flows through the P-type heavily doped region 161 in the P-type well 12 and increases the potential of the P-type well 12 at the same time, leading to the turn-on of a lateral parasitic transistor shown in FIG. 3.
The lateral parasitic transistor is a NPN transistor composed of the N-type lightly doped region 11, the P-type well 12 below the LDMOS channel and the source 162. When ESD occurs, this lateral parasitic transistor will be turned on for discharging current.
However, as the pervious research finds: after the lateral parasitic transistor is turned on, the current from the drain 163 flows mainly through the N-type lightly doped region 11 below the isolation structure 133 which is partly covered by the gate 14 to the border of the N-type lightly doped region 11 below the entire LDMOS channel and further into the P-type well 12.
Therefore, the potential of the N-type lightly doped region 11 below the P-type heavily doped region 164 is difficult to fall by a value, e.g. 0.7V to turn on the vertical parasitic transistor shown in FIG. 3, which leads to a situation that when the vertical parasitic transistor is turned on, the lateral parasitic transistor has been turned on completely. The vertical parasitic transistor is a PNP transistor composed of the P-type heavily doped region 164, the N-type lightly doped region 11 and the P-type well 12.
The current of the lateral parasitic transistor flows close to the surface of the LDMOS device, and the electric field strength at the border of the drain 163 and the isolation structure 133 is large. Under the influence of the large surface current and electric field strength, the heating power at the intersection point of the surface and the border is large. Therefore, generally, before the vertical parasitic transistor is turned on, damage has occurred at this intersection point shown as the early damage point B in FIG. 2.
Besides, the voltage breakdown may occur on the other side of the N-type lightly doped region 11, that is the side close to the P-type heavily doped region 164, through adjusting the distance C (shown in FIG. 3) between the borders of the P-type heavily doped region 164 and the N-type lightly doped region 11, so that the appearance of the early failure point A may be avoided. However, this adjustment may lead to an unstable avalanche breakdown voltage and therefore forms an unstable electrostatic trigger voltage therefrom.